Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 3)

Some brief theory and typical measurements of phase noise. How to produce the lowest phase noise at a PLL output. A standard design procedure for a typical Type 2, second-order loop. As stated in ...
Electronics Weekly

Great phase-locked loop motor control app note

Related to my search for reduced motor noise (and thanks to all who have made suggestions – ‘scope avaunt this weekend), is a search for speed stability in that motor*. And to someone who is in love ...
Hackaday

Unlock The Phase Locked Loop

If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise ...
EDN

FPGA-Based DPLL Approach Delivers Wide-Lock Range

While analog phase-lock loops (PLLs) still have a home in communication equipment, there is a clear shift in the sector toward implementing digital PLLs (DPLLs) in comm ASIC designs. For example, in ...
Science Daily

Digital phase-locked loop achieves a power consumption of 0.265 mW

Scientists have developed an advanced phase-locked loop (PLL) frequency synthesizer that can drastically cut power consumption. This digital PLL could be an attractive building block for Bluetooth Low ...
Electronics Weekly

Lockdown project: Enter the 9046 – the ultimate ‘4046’ phase-locked loop

I had never heard of the 74HCT9046 phase-locked loop before a fortnight ago, and now I own one. To my shame, it was apparently released by Phillips (now Nexperia) around 20 years ago – that said, the ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 1)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...